pre-production this is a product in the pre-production phase of development. device ramtron international corporation characterization is complete and ramtron does not expect to change 1850 ramtron drive, colorado springs, co 80921 the specifications. ramtron will issue a product change notice if any (800) 545-fram, (719) 481-7000 specification changes are made. http://www.ramtron.com rev. 2.0 feb. 2008 page 1 of 8 fm1114 nonvolatile 3v quad state saver features nonvolatile state saver ? logic states retained in absence of power ? outputs automatically restored at power-up ? unlimited number of state changes ? max t pd 50ns at 2.7v ? max frequency 1 mhz low power operation ? supply voltage of 2.7v to 3.6v ? 0.5 a standby current industry standard configuration ? industrial temperature -40 c to +85 c ? 16-pin ?green?/rohs qfn package overview the fm1114 is an innovative fram-based device that stores inputs like conventional logic and retains the stored state in the absence of power. this product solves three basic problems in an elegant fashion. first, it provides continuous access to nonvolatile system settings without performing a memory read operation or using dedicated processor i/o pins. second, it allows the storage of signals that may change frequently and possibly without notice. third, it allows the nonvolatile storage of a system setting without the system overhead and extra pins of a serial memory. functionally, the inputs are stored and passed to the output on the rising edge of the clock clk. this unique product serves a variety of applications. here are a few applications: ! control relays or valves with automatic setting on power-up without processor intervention ! interface to soft/momentary front-panel switch and indicator lamp. capture switch settings and drive leds without processor intervention ! replaces jumpers & control signal routing ! initialize state of i/o card signals ! eliminate the overhead of serial memory for systems needing only a bit of data pin configuration pin names function d n data in q n data out en enable clk clock vdd supply voltage vss ground ordering information fm1114-qg quad state saver, 16-pin ?green?/rohs qfn top view vdd d0 q0 d1 q2 d2 d3 vss 1 2 3 4 q1 vss clk q3 7 15 11 nc nc vdd en
fm1114 nv quad state saver rev. 2.0 feb. 2008 page 2 of 8 block diagram and truth table inputs en clk dn output qn h l l h h h h h or l x q 0 l x x hi-z l low voltage level h high voltage level x don?t care clk rising edge q 0 previous output state before clk pin descriptions pin name i/o description d(3:0) i data inputs q(3:0) o data outputs clk i clock: on a rising edge of clk, the d n inputs are transferred to the q n outputs. while clk is high or low, the q n outputs do not change regardless of the state of the data inputs. see truth table. en i enable. this active-high input enables the device. when low, inputs are ignored and updates to the nonvolatile cells are prevented. when high, the device operates normally. do not tie this pin to v dd . vdd supply power supply (2.7v to 3.6v) vss supply ground nv state saver clk d n q n en
fm1114 nv quad state saver rev. 2.0 feb. 2008 page 3 of 8 description nonvolatile storage applied to logic is a revolutionary concept. the fm1114 simplifies the design of system control functions. this product is unique because it remembers the stored output values in the absence of power. any change in the latched state is automatically written to a nonvolatile ferroelectric latch. this function is possible due to the fast write time and extremely high write endurance of the underlying ferroelectric memory technology. use of enable pin the fm1114 has an enable pin that is intended to be used in conjunction with a system reset. an active- low reset may be tied directly to the en pin. at power-up, /reset will be held low for some time during which the data input and clk pins will be ignored. once the system comes out of reset and en goes high, the outputs q n drive to the state that were previously latched and the device operates normally. when the en pin is low, the outputs q n are tri- stated. the enable pin must not be tied to v dd because the device does not have any power management circuits to monitor v dd . the enable input must be held low during power cycles.
fm1114 nv quad state saver rev. 2.0 feb. 2008 page 4 of 8 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +5.0v v in voltage on any signal pin with respect to v ss -1.0v to +5.0v and v in < v dd +1.0v t stg storage temperature -55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 300 c v esd electrostatic discharge voltage - human body model (jedec std jesd22-a114-b) - charged device model (jedec std jesd22-c101-a) - machine model (jedec std jesd22-a115-a) tbd tbd tbd package moisture sensitivity level tbd stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions ( t a = -40 c to + 85 c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 2.7 - 3.6 v i sb standby current - 0.5 a 1 c pd power dissipation capacitance - 330 pf 2 i li input leakage current 1 a 3 i lo output leakage current 1 a 3 v il input low voltage -0.3 0.3 v dd v v ih input high voltage 0.7 v dd v dd + 0.3 v v oh output high voltage @ i oh = -1 ma v dd ? 0.5 - v v ol output low voltage @ i ol = 1 ma (v dd =2.7v) @ i ol = 10 ma (v dd =2.7v) - - 0.4 0.8 v v v hys input hysteresis (clk, en) 200 mv 4 notes 1. clk = v ss , all other inputs at v dd or v ss . 2. to calculate device power dissipation, p d = c pd *v dd 2 *f i + c l *v dd 2 *f o , where f i is the input clk freq, f o is the output freq, and c l is the output load capacitance. active current i dd may be calculated as i dd = c pd *v dd *f i , assuming outputs are floating. 3. v in or v out = v ss to v dd . 4. this parameter is characterized but not tested.
fm1114 nv quad state saver rev. 2.0 feb. 2008 page 5 of 8 ac parameters (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v, c l = 30 pf unless otherwise specified) symbol parameter min max units notes f max maximum clock frequency 1 mhz t low clk low period 0.3 s t high clk high period 0.3 s t pd propagation delay clk to q n 50 ns t hz en low to q n hi-z 25 ns 1 t r input rise time 100 ns 1 t f input fall time 100 ns 1 t ds data (d n ) setup time to clk 5 ns t dh data (d n ) hold time after clk 10 ns t ehd en hold time (en high after clk ) 50 - ns t eh en high time 5 s t el en low time 2 s notes 1. this parameter is characterized but not tested. power cycling and data retention (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v, unless otherwise specified) symbol parameter min max units notes nonvolatile data retention time 45 - years t vdr v dd rise time 0.1 - s/v 1 t vdf v dd fall time 0.1 - s/v 1 t res en high to q n restore time - 0.5 s 2 t pds en low to power down time 1 - s t ehfc en high to first clock (clk ) after power up 4 - s 3 notes 1. slope measured at any point on v dd waveform. 2. after power up, when en goes high the nonvolatile latches are read and the values restored to the outputs q n . 3. after power up, this is the minimum time required before a state change operation may occur. en and v dd may be coincident at power up, and in this case t ehfc time is referenced to v dd (min) and clk . capacitance (t a = 25 c , f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c i input capacitance - 14 pf 1 notes 1. this parameter is characterized but not tested.
fm1114 nv quad state saver rev. 2.0 feb. 2008 page 6 of 8 ac test conditions input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd output load capacitance 30pf fm1114 signal timing clk d n q n previous d0 q0 t pd t ds t dh t high 1/f max d1 t low t=0 en t ehd q1 t pd t hz t el t eh q1 t res power cycle timing ~ ~ ~ ~ ~ ~ d7 d8 dlast q7 q8 qlast qlast d0 d1 q0 q1 clk d n q n ~ ~ v dd v dd (min) v dd (min) t pds t ehfc t res ~ ~ en
fm1114 nv quad state saver rev. 2.0 feb. 2008 page 7 of 8 mechanical drawing 16-pin qfn (4.0mm x 4.0mm body, 0.65mm pitch) pin 1 4.0 0.1 4.0 0.1 0.75 0.05 0.65 typ 0.20 ref. 0.0 - 0.05 0.55 0.10 pin 1 id exposed metal pad. do not connect to anything except vss. 0.65 typ 1 2 3 4 2.20 2.00 0.30 0.05 1.95 ref note: all dimensions in millimeters . care must be taken to ensure pcb traces and vias are not placed within the exposed metal pad area. qfn package marking scheme legend: xxxx=base part number, pp=package designator (q=qfn, g=?green?) llllll= lot code yy=year, ww=work week example: fm1114, ?green? qfn package, lot 0001, year 2007, work week 32 1114qg 0001 0732 xxxxpp llllll yyww
fm1114 nv quad state saver rev. 2.0 feb. 2008 page 8 of 8 revision history revision date summary 1.0 8/8/2007 initial release. 1.1 8/22/2007 reduced i sb spec. 2.0 2/20/2008 changed to pre-production status. changed v hys and t ehd (min.) limits.
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